Degenerator DIY Sampler/Synthesizer (Tubeohm)

//*************************************************************************
// DMA init
//*************************************************************************
void dma_init(void){
    DMA.CTRL = DMA_CH_ENABLE_bm | DMA_DBUFMODE_CH01CH23_gc; // set Double Buffer and enabled
    
    // DMA Channel 0 (Audio-Buffer A)   
    DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc
    | DMA_CH_DESTRELOAD_BURST_gc | DMA_CH_DESTDIR_INC_gc;
    DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_DACB_CH0_gc; // DACB CH0 is trigger Quelle
    DMA.CH0.DESTADDR0 = (((uint32_t)(&DACB.CH0DATAH))>>0*8) & 0xFF;
    DMA.CH0.DESTADDR1 = (((uint32_t)(&DACB.CH0DATAH))>>1*8) & 0xFF;
    DMA.CH0.DESTADDR2 = (((uint32_t)(&DACB.CH0DATAH))>>2*8) & 0xFF;
    DMA.CH0.TRFCNT = 128;
    DMA.CH0.SRCADDR0 = (((uint32_t)(&Voice.Buffer_A))>>0*8) & 0xFF;
    DMA.CH0.SRCADDR1 = (((uint32_t)(&Voice.Buffer_A))>>1*8) & 0xFF;
    DMA.CH0.SRCADDR2 = (((uint32_t)(&Voice.Buffer_A))>>2*8) & 0xFF;
    DMA.CH0.CTRLA = 0xA4;   // Aktivieren, Wiederholen, 1 Byte, Single
    
    // DMA Channel 1 (Audio-Buffer B)
    DMA.CH1.ADDRCTRL = DMA_CH_SRCRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc
    | DMA_CH_DESTRELOAD_BURST_gc | DMA_CH_DESTDIR_INC_gc;
    DMA.CH1.TRIGSRC = DMA_CH_TRIGSRC_DACB_CH0_gc; // DACB CH0 is trigger Quelle
    DMA.CH1.DESTADDR0 = (((uint32_t)(&DACB.CH0DATAH))>>0*8) & 0xFF;
    DMA.CH1.DESTADDR1 = (((uint32_t)(&DACB.CH0DATAH))>>1*8) & 0xFF;
    DMA.CH1.DESTADDR2 = (((uint32_t)(&DACB.CH0DATAH))>>2*8) & 0xFF;
    DMA.CH1.TRFCNT = 128;
    DMA.CH1.SRCADDR0 = (((uint32_t)(&Voice.Buffer_B))>>0*8) & 0xFF;
    DMA.CH1.SRCADDR1 = (((uint32_t)(&Voice.Buffer_B))>>1*8) & 0xFF;
    DMA.CH1.SRCADDR2 = (((uint32_t)(&Voice.Buffer_B))>>2*8) & 0xFF;
    DMA.CH1.CTRLA = 0xA4;   // Aktivieren, Wiederholen, 1 Byte, Single
    
    // DMA Channel 2 (Audio-Buffer C)
    DMA.CH2.ADDRCTRL = DMA_CH_SRCRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc
    | DMA_CH_DESTRELOAD_BURST_gc | DMA_CH_DESTDIR_INC_gc;
    DMA.CH2.TRIGSRC = DMA_CH_TRIGSRC_DACA_CH0_gc; // DACA CH0 is trigger Quelle
    DMA.CH2.DESTADDR0 = (((uint32_t)(&DACA.CH0DATAH))>>0*8) & 0xFF;
    DMA.CH2.DESTADDR1 = (((uint32_t)(&DACA.CH0DATAH))>>1*8) & 0xFF;
    DMA.CH2.DESTADDR2 = (((uint32_t)(&DACA.CH0DATAH))>>2*8) & 0xFF;
    DMA.CH2.TRFCNT = 128;
    DMA.CH2.SRCADDR0 = (((uint32_t)(&Voice.Buffer_C))>>0*8) & 0xFF;
    DMA.CH2.SRCADDR1 = (((uint32_t)(&Voice.Buffer_C))>>1*8) & 0xFF;
    DMA.CH2.SRCADDR2 = (((uint32_t)(&Voice.Buffer_C))>>2*8) & 0xFF;
    DMA.CH2.CTRLA = 0xA4;   // Aktivieren, Wiederholen, 1 Byte, Single
    
    // DMA Channel 3 (Audio-Buffer D)
    DMA.CH3.ADDRCTRL = DMA_CH_SRCRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc
    | DMA_CH_DESTRELOAD_BURST_gc | DMA_CH_DESTDIR_INC_gc;
    DMA.CH3.TRIGSRC = DMA_CH_TRIGSRC_DACA_CH0_gc; // DACA CH0 is trigger Quelle
    DMA.CH3.DESTADDR0 = (((uint32_t)(&DACA.CH0DATAH))>>0*8) & 0xFF;
    DMA.CH3.DESTADDR1 = (((uint32_t)(&DACA.CH0DATAH))>>1*8) & 0xFF;
    DMA.CH3.DESTADDR2 = (((uint32_t)(&DACA.CH0DATAH))>>2*8) & 0xFF;
    DMA.CH3.TRFCNT = 128;
    DMA.CH3.SRCADDR0 = (((uint32_t)(&Voice.Buffer_D))>>0*8) & 0xFF;
    DMA.CH3.SRCADDR1 = (((uint32_t)(&Voice.Buffer_D))>>1*8) & 0xFF;
    DMA.CH3.SRCADDR2 = (((uint32_t)(&Voice.Buffer_D))>>2*8) & 0xFF;
    DMA.CH3.CTRLA = 0xA4;   // Aktivieren, Wiederholen, 1 Byte, Single
}


//*************************************************************************
// Timer0 Interrupt: DAC Task 40KHz/25usec
//*************************************************************************
ISR(TCC0_OVF_vect)
{   
    // DMA Interrupt ------------------------------------------------------
    
    // if Channel Transaction Complete Interrupt Flag set
    if (DMA.INTFLAGS & DMA_CH0TRNIF_bm)
    {
        // set buffer_nr
        Voice.buffer_nr = 0;
        
        // set buffer_fill interrupt
        TCE1.INTCTRLA = 0b00000010;
        
        // clear DMA Interrupt (set one)
        DMA.INTFLAGS |= DMA_CH0TRNIF_bm;
    }
    else if (DMA.INTFLAGS & DMA_CH1TRNIF_bm)
    {
        // set buffer_nr
        Voice.buffer_nr = 1;
        
        // set buffer_fill interrupt
        TCE1.INTCTRLA = 0b00000010;
        
        // clear DMA Interrupt (set one)
        DMA.INTFLAGS |= DMA_CH1TRNIF_bm;
    }

....

uint16_t RNG_16;
uint8_t RNG_8;

static inline Noise8(void) {
    asm volatile (
    "lds r30, RNG_16+0" "\n\t"
    "lds r31, RNG_16+1" "\n\t"
    "lsr r31" "\n\t"
    "ror r30" "\n\t"
    "brsh xxor" "\n\t"
    "ldi r17, 0xb4" "\n\t"
    "xxor: eor r31, r17" "\n\t"
    "sts RNG_8, r30" "\n\t"
    "sts RNG_16+0, r30" "\n\t"
    "sts RNG_16+1, r31" "\n\t"
    ::: "r17", "memory"
    );
}